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| Preliminary FM23MLD16 8Mbit F-RAM Memory Features 8Mbit Ferroelectric Nonvolatile RAM * Organized as 512Kx16 * Configurable as 1Mx8 Using /UB, /LB * High Endurance 100 Trillion (1014) Read/Writes * NoDelayTM Writes * Page Mode Operation to 33MHz * Advanced High-Reliability Ferroelectric Process SRAM Compatible * JEDEC 512Kx16 SRAM Pinout * 60 ns Access Time, 115 ns Cycle Time Advanced Features * Low VDD Monitor Protects Memory against Inadvertent Writes Superior to Battery-backed SRAM Modules * No Battery Concerns * Monolithic Reliability * True Surface Mount Solution, No Rework Steps * Superior for Moisture, Shock, and Vibration Low Power Operation * 2.7V - 3.6V Power Supply * 14 mA Active Current Industry Standard Configuration * Industrial Temperature -40 C to +85 C * 48-pin "Green"/RoHS FBGA package Description The FM23MLD16 is a 512Kx16 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and very high write endurance make F-RAM superior to other types of memory. In-system operation of the FM23MLD16 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. Read and write cycles may be triggered by a chip enable or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM23MLD16 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. The FM23MLD16 includes a low voltage monitor that blocks access to the memory array when VDD drops below a critical threshold. The memory is protected against an inadvertent access and data corruption under this condition. The FM23MLD16 F-RAM is available in a 48-ball FBGA surface mount package. Device specifications are guaranteed over the industrial temperature range of -40C to +85C. 48-Ball FBGA Top View (Ball Down) 1 2 3 4 5 6 A B C D E F G H /LB /OE A0 A1 A2 CE2 DQ8 /UB A3 A4 /CE1 DQ0 DQ9 DQ10 A5 A6 DQ1 DQ2 VSS DQ11 A17 A7 DQ3 VDD VDD DQ12 NC A16 DQ4 VSS DQ14 DQ13 A14 A15 DQ5 DQ6 DQ15 NC A12 A13 /WE DQ7 A18 A8 A9 A10 A11 NC Ordering Information FM23MLD16-60-BG 60 ns access, 48-pin "Green"/RoHS FBGA This is a product that has fixed target specifications but are subject to change pending characterization results. Rev. 1.0 Dec. 2008 Ramtron International Corporation 1850 Ramtron Drive, Colorado Springs, CO 80921 (800) 545-FRAM, (719) 481-7000 http://www.ramtron.com Page 1 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Address Latch Figure 1. Block Diagram Pin Description Pin Name Type A(18:0) Input /CE1, CE2 Input /WE Input /OE DQ(15:0) /UB /LB VDD VSS Input I/O Input Input Supply Supply Pin Description Address inputs: The A(17:0) address lines select one of 262,144 words in each of the FRAM die. A18 selects one of the two die. The lowest two address lines A(1:0) may be used for page mode read and write operations. Chip Enable inputs: The device is selected and a new memory access begins on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The entire address is latched internally at this point. Write Enable: A write cycle begins when /WE is asserted. The rising edge causes the FM23MLD16 to write the data on the DQ bus to the F-RAM array. The falling edge of /WE latches a new column address for page mode write cycles. Output Enable: When /OE is low, the FM23MLD16 drives the data bus when valid read data is available. Deasserting /OE high tri-states the DQ pins. Data: 16-bit bi-directional data bus for accessing the F-RAM array. Upper Byte Select: Enables DQ(15:8) pins during reads and writes. These pins are hi-Z if /UB is high. Lower Byte Select: Enables DQ(7:0) pins during reads and writes. These pins are hi-Z if /LB is high. Supply Voltage: 3.3V Ground Rev. 1.0 Dec. 2008 Chip & Row Decoder Page 2 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Functional Truth Table 1 /CE1 CE2 /WE H X X X L X H H H L L H H L H H H L L L L H L H H X X L Notes: 1) 2) 3) 4) A(18:2) X X V V No Change Change V V V No Change X X A(1:0) X X V V Change V V V V V X X Operation Standby/Idle Read Page Mode Read Random Read /CE-Controlled Write 2 /WE-Controlled Write 2, 3 Page Mode Write 4 Starts Precharge H=Logic High, L=Logic Low, V=Valid Data, X=Don't Care. For write cycles, data-in is latched on the rising edge of /CE1 or /WE of the falling edge of CE2, whichever comes first. /WE-controlled write cycle begins as a Read cycle and A(18:3) is latched then. Addresses A(2:0) must remain stable for at least 15 ns during page mode operation. Byte Select Truth Table /OE /LB /UB H X X X H H L H L L H L L X H L L H L L Operation Read; Outputs Disabled Read; DQ(7:0) Hi-Z Read; DQ(15:8) Hi-Z Read Write; Mask DQ(7:0) Write; Mask DQ(15:8) Write Rev. 1.0 Dec. 2008 Page 3 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Overview The FM23MLD16 is a wordwide F-RAM memory logically organized as 524,288 x 16 and accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a different page is triggered by toggling a chip enable pin or simply by changing the upper address A(18:2). Write Operation Writes occur in the FM23MLD16 in the same time interval as reads. The FM23MLD16 supports both /CE- and /WE-controlled write cycles. In both cases, the address A(18:2) is latched on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when the device is activated with a chip enable. In this case, the device begins the memory cycle as a write. The FM23MLD16 will not drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when the device is deselected with a chip enable. In a /WE-controlled write, the memory cycle begins when the device is activated with a chip enable. The /WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is asserted low. The /CE- and /WE-controlled write timing cases are shown in the Electrical Specifications section. In the Write Cycle Timing 2 diagram, the data bus is shown as a hi-Z condition while the chip is write-enabled and before the required setup time. Although this is drawn to look like a mid-level voltage, it is recommended that all DQ pins comply with the minimum VIH/VIL operating levels. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the deassertion of /WE, /CE1, or CE2, whichever comes first. A valid write operation requires the user to meet the access time specification prior to deasserting /WE, /CE1, or CE2. Data setup time indicates the interval during which data cannot change prior to the end of the write access (rising edge of /WE or the chip is deselected with /CE1 or CE2). Unlike other truly nonvolatile memory technologies, there is no write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM23MLD16 provides the user fast access to any data within a row element. Each row has 4 column address locations. Address inputs A(1:0) define the column address to be accessed. An access can start on any column address, and other column Page 4 of 13 Memory Operation Users access 524,288 memory locations, each with 16 data bits through a parallel interface. The F-RAM memory is organized as 2 die each having 64K rows. Each row has 4 column locations, which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low), subsequent column locations may be accessed without the need to toggle a chip enable. When either chip enable pin is deasserted, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to F-RAM called NoDelayTM writes. Read Operation A read operation begins on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The /CE-initiated access causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the access time has been satisfied. Once the address has been latched and the access completed, a new access to a random location (different row) may begin while both chip enables are still active. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM23MLD16's /CEinitiated access time is faster than the address cycle time. The FM23MLD16 will drive the data bus when /OE and at least one of the byte enables (/UB, /LB) is asserted low. The upper data byte is driven when /UB is low, and the lower data byte is driven when /LB is low. If /OE is asserted after the memory access time has been satisfied, the data bus will be driven with valid data. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is deasserted high, the data bus will remain in a high-Z state. Rev. 1.0 Dec. 2008 FM23MLD16 - 512Kx16 FRAM (multi die) locations may be accessed without the need to toggle the CE pins. For fast access reads, once the first data byte is driven onto the bus, the column address inputs A(1:0) may be changed to a new value. A new data byte is then driven to the DQ pins no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. While the device is selected (both chip enables asserted), a subsequent write pulse along with a new column address provides a page mode write access. Precharge Operation The precharge operation is an internal condition in which the state of the memory is being prepared for a new access. Precharge is user-initiated by driving at least one of the chip enable signals to an inactive state. It must remain high for at least the minimum precharge time tPC. For applications that require the lowest power consumption, the /CE1 signal should be active only during memory accesses. The FM23MLD16 draws supply current while /CE1 is low, even if addresses and control signals are static. While /CE1 is high, the device draws no more than the maximum standby current ISB. Note that if /CE1 is grounded and CE2 tied to VDD, the user must be sure /WE is not low at powerup or powerdown events. If the chip is enabled and /WE is low during power cycles, data corruption will occur. Figure 3 shows a pullup resistor on /WE which will keep the pin high during power cycles assuming the MCU/MPU pin tri-states during the reset condition. The pullup resistor value should be chosen to ensure the /WE pin tracks VDD yet a high enough value that the current drawn when /WE is low is not an issue. A 10Kohm resistor draws 330uA when /WE is low and VDD=3.3V. VDD R MCU/ MPU FM23MLD16 CE2 CE1 WE OE A(18:0) DQ(15:0) SRAM Drop-In Replacement The FM23MLD16 has been designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require the CE pins to toggle for each new address. Both CE pins may remain active indefinitely. When both CE pins are active, the device automatically detects address changes and a new access is begun. This functionality allows the chip enable pins to be tied active (/CE1 grounded, CE2 tied to VDD) as you might with an SRAM. It also allows page mode operation at speeds up to 33MHz. A typical application is shown in Figure 2. It shows a pullup resistor on /CE1 which will keep the pin high during power cycles assuming the MCU/MPU pin tristates during the reset condition. The pullup resistor value should be chosen to ensure the /CE1 pin tracks VDD yet a high enough value that the current drawn when /CE1 is low is not an issue. Although not required, it is recommended that CE2 be tied to VDD if the controller provides an active-low chip enable. VDD FM23MLD16 R CE2 CE1 Figure 3. Use of Pullup Resistor on /WE The /UB and /LB byte select pins are active for both read and write cycles. They may be used to allow the device to be wired as a 1Mx8 memory. The upper and lower data bytes can be tied together and controlled with the byte selects. Individual byte enables or the next higher address line A(19) may be available from the system processor. MCU/ MPU WE OE A(18:0) DQ(15:0) Figure 2. Typical Application using Pullup Resistor on /CE1 Rev. 1.0 Dec. 2008 Figure 4. FM23MLD16 Wired as 1Mx8 Page 5 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) PCB Layout Recommendations A 0.1uF decoupling capacitor should be placed close to each power/ground pair (solder balls 1D/1E and 6D/6E). The ground side of the capacitor should be connected to either a ground plane or low impedance path back to the VSS pins. It is best to use a chip capacitor that has low ESR and has good high frequency characteristics. If the controller drives the address and chip enable from the same timing edge, it is best to keep the address routes short and of equal length. A simple RC circuit may be inserted in the chip enable path to provide some delay and timing margin for the FM23MLD16's address setup time tAS. As a general rule, the layout designer may need to add series termination resistors to controller outputs that have fast transitions or routes that are > 15cm in length. This is only necessary if the edge rate is less than or equal to the round trip trace delay. Signal overshoot and ringback may be large enough to cause erratic device behavior. It is best to add a 50 ohm resistor (30 - 60 ohms) near the output driver (controller) to reduce such transmission line effects. Rev. 1.0 Dec. 2008 Page 6 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Electrical Specifications Absolute Maximum Ratings Symbol Description VDD Power Supply Voltage with respect to VSS VIN Voltage on any signal pin with respect to VSS TSTG TLEAD VESD Storage Temperature Lead Temperature (Soldering, 10 seconds) Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-D) - Charged Device Model (JEDEC Std JESD22-C101-C) - Machine Model (JEDEC Std JESD22-A115-A) Package Moisture Sensitivity Level Ratings -1.0V to +4.5V -1.0V to +4.5V and VIN < VDD+1V -55C to +125C 300 C TBD TBD TBD MSL-3 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 2.7 3.3 3.6 V IDD Power Supply Current 9 14 mA 1 2 ISB Standby Current 300 180 @ TA = 25C A 540 @ TA = 85C A VTP VDD Trip Point to Block Accesses 2.2 2.6 V 3 ILI Input Leakage Current 1 A ILO Output Leakage Current 1 A VIH Input High Voltage 2.2 VDD + 0.3 V VIL Input Low Voltage -0.3 0.6 V VOH1 Output High Voltage (IOH = -1.0 mA) 2.4 V VOH2 Output High Voltage (IOH = -100 A) VDD-0.2 V VOL1 Output Low Voltage (IOL = 2.1 mA) 0.4 V VOL2 Output Low Voltage (IOL = 100 A) 0.2 V Notes 1. VDD = 3.6V, CE pin(s) cycling at min. cycle time. All inputs toggling at CMOS levels (0.2V or VDD-0.2V), all DQ pins 2. 3. unloaded. VDD = 3.6V, /CE1 at VDD or CE2 at VSS, all other pins are static and at CMOS levels (0.2V or VDD-0.2V). If VDD < VTP, all memory accesses are blocked regardless of input pin conditions. Rev. 1.0 Dec. 2008 Page 7 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Read Cycle AC Parameters (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units tRC Read Cycle Time 115 ns tCE Chip Enable Access Time 60 ns tAA Address Access Time 115 ns tOH Output Hold Time 25 ns tAAP Page Mode Address Access Time 25 ns tOHP Page Mode Output Hold Time 5 ns tCA Chip Enable Active Time 60 ns tPC Precharge Time 55 ns tBA /UB, /LB Access Time 20 ns tAS Address Setup Time (to /CE1, CE2 active) 0 ns tAH Address Hold Time (CE-controlled) 60 ns tOE Output Enable Access Time 15 ns tHZ Chip Enable to Output High-Z 10 ns tOHZ Output Enable High to Output High-Z 10 ns tBHZ /UB, /LB High to Output High-Z 10 ns Notes 1 1 1 Write Cycle AC Parameters (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes tWC Write Cycle Time 115 ns tCA Chip Enable Active Time 60 ns tCW Chip Enable to Write Enable High 60 ns tPC Precharge Time 55 ns tBHZ /UB, /LB High to Output High-Z 5 ns tPWC Page Mode Write Enable Cycle Time 25 ns tWP Write Enable Pulse Width 16 ns tAS Address Setup Time (to /CE1, CE2 active) 0 ns tASP Page Mode Address Setup Time (to /WE low) 8 ns tAHP Page Mode Address Hold Time (to /WE low) 15 ns tWLC Write Enable Low to Chip Disabled 25 ns tWLA Write Enable Low to A(18:2) Change 25 ns tAWH A(18:2) Change to Write Enable High 115 ns tDS Data Input Setup Time 14 ns tDH Data Input Hold Time 0 ns tWZ Write Enable Low to Output High Z 10 ns 1 tWX Write Enable High to Output Driven 10 ns 1 tWS Write Enable to /CE Low Setup Time 0 ns 2 tWH Write Enable to /CE High Hold Time 0 ns 2 Notes 1 This parameter is characterized but not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. The parameters tWS and tWH are not tested. Capacitance Symbol CI/O CIN1 CIN2 (TA = 25 C , f=1 MHz, VDD = 3.3V) Parameter Input/Output Capacitance (all DQ) Input Capacitance (/CE1, CE2, A18) Input Capacitance (A17-A0, /WE, /OE, /LB, /UB) Min - Max 16 6 12 Units pF pF pF Notes Rev. 1.0 Dec. 2008 Page 8 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Power Cycle Timing (TA = -40 C to + 85 C, VDD = 2.7V to 3.6V unless otherwise specified) Symbol Parameter Min Max tPU Power-Up to First Access Time (after VDD min) 450 tPD Last Write (/WE high) to Power Down Time (prior to VTP) 0 tVR VDD Rise Time 50 tVF VDD Fall Time 100 - Units s s s/V s/V Notes 1,2 1,2 Notes 1 Slope measured at any point on VDD waveform. 2 Ramtron cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict when VDD is below the level of a transistor threshold voltage. Ramtron strongly recommends that VDD power up faster than 100ms through the range of 0.4V to 1.0V. Data Retention (VDD = 2.7V to 3.6V) Parameter Data Retention Min 10 Units Years Notes AC Test Conditions Input Pulse Levels Input Rise and Fall Times 0 to 3V 3 ns Input and Output Timing Levels Output Load Capacitance 1.5V 30pF Read Cycle Timing 1 (/CE1 low, CE2 high, /OE low) Read Cycle Timing 2 (/CE-controlled) Rev. 1.0 Dec. 2008 Page 9 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Page Mode Read Cycle Timing 1. Although sequential column addressing is shown, it is not required. Write Cycle Timing 1 (/WE-Controlled, /OE low) tCA tCW tPC CE1 CE2 tAS tWLC A(18:0) tWP WE tWZ tDH tDS D in tWX tHZ DQ(15:0) Write Cycle Timing 2 (/CE-Controlled) D out D out Rev. 1.0 Dec. 2008 Page 10 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Write Cycle Timing 3 (/CE1 low, CE2 high) Page Mode Write Cycle Timing 1. Although sequential column addressing is shown, it is not required. Rev. 1.0 Dec. 2008 Page 11 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Mechanical Drawing 48-ball FBGA (0.75mm ball pitch) Top View 6 Bottom View 5 4 3 2 1 Pin A1 0.75 typ A B C D E F G 8.00 BSC 0.400.05 H 1.875 6.00 BSC 6.00 BSC 1.20 max 0.25 0.10 mm Note: All dimensions in millimeters. 48 FBGA Package Marking Scheme RAMTRON XXXXXXX-S-P LLLLLLL YYWW Legend: XXXXXX= part number, S=speed, P=package LLLLLL= lot code, YY=year, WW=work week Examples: FM23MLD16, "Green"/RoHS FBGA package, Lot C8556953BG1, Year 2008, Work Week 44 RAMTRON FM23MLD16-60-BG C8556953BG1 0844 Rev. 1.0 Dec. 2008 Page 12 of 13 FM23MLD16 - 512Kx16 FRAM (multi die) Revision History Revision 1.0 Date 12/12/2008 Summary Initial release. Rev. 1.0 Dec. 2008 Page 13 of 13 |
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